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DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
BIT DESCRIPTION
RST: Reset Flag
WDA: Watchdog Alarm
CLKA: Clock Alarm
BOR: Battery-On Reset
Flag
POR: Power-On Reset
Flag
WPZV: Hardware Write
Protect Value
BATA: Battery Alarm
BIT(S)
b0
b1
b2
b3
b4
b5
b6
DEFINITION
RSTZ pin activity indicator; set whenever there is a pulse at RSTZ;
cleared by writing to the Alarm and Status register.
V CC ramp up: 1; V BAT attach: 0
Watchdog Alarm indicator; set whenever the watchdog is enabled AND
the watchdog timer expires; cleared by writing to the Alarm and Status
register.
V CC ramp up: 0; V BAT attach: 0
RTC /Calendar Alarm indicator; set whenever the clock alarm is enabled
AND RTC and RTC Alarm register match; cleared by writing to the
Alarm and Status register.
V CC ramp up: 0; V BAT attach: 0
Battery attach indicator; set whenever the voltage at V BAT ramps up
above V BATmin ; cleared by writing to the Alarm and Status register.
V CC ramp up: not affected; V BAT attach: 1
Power-On Reset indicator; set whenever the voltage at V CC ramps up
above V CCmin ; cleared by writing to the Alarm and Status register.
V CC ramp up: 1; V BAT attach: 0
WPZ pin state readout; reports the logic state at the WPZ pin;
V CC ramp up: WPZ pin state; V BAT attach: not affected.
Low Battery indicator; set whenever the battery alarm is enabled AND if,
during a battery test, V BAT is below the selected V BAT trip point; cleared
by writing to the Alarm and Status register.
V CC ramp up: battery test if BME = 1; V BAT attach: 0
Figure 5. ALMZ, WDOZ, and RSTZ Generation
BME
BATA
CAE
ALMZ
CLKA
WDOZ
WDE
WDA
WDOS
RSTZ
VCLA
Debounce
BME, CAE, WDE, WDOS are defined in the Control/Setup register.
BATA, CLKA, WDA are alarm signals readable through the Alarm/Status register.
VCLA is the alarm output of the V CC monitor.
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